The present invention relates to the manufacture of CMOS integrated circuits. Specifically, a method for designing integrated circuits which prevents an excessive electrostatic charge from accumulating on circuit conductors during manufacture is described.
Custom CMOS integrated circuit technologies require a processing step which is known as a Reactive Ion Etch (RIE) to process the various metal layers of an integrated circuit. In the ASIC (Application Specific Integrated Circuit) environment for manufacturing custom logic circuits, components such as processors, memory arrays, and input and output interface circuits are integrated in a custom circuit and interconnected by metal wiring layers. The RIE process for establishing the connections of a layer may result in electrostatic charge being built up on the metal lines of each layer which may be applied to the transistor gates permanently damaging the transistor.
The problem of electrostatic charge building up on metal lines during fabrication is well known and numerous solutions have been proposed. Various techniques have been employed to reduce or dissipate the charge as it builds up on the metal lines to avoid damaging the connected transistor. A common charge dissipation technique is to build floating gate diodes on each circuit input pin, which connects to a gate, to slowly bleed off the electrostatic charge as it accumulates on the metal line. However, as circuit densities increase, it is more difficult to find sufficient surface area for locating floating gate diodes, whose only function is to protect the gates during manufacture. The floating gate diodes remain as permanent circuit elements adversely affecting performance and power dissipation of the integrated circuit.
Instead of placing floating gate diodes on each input pin, the full chip designs may be checked before implementation into silicon for potential problem areas where charge is likely to build up during fabrication. An antenna rule has been devised to identify locations within the metalization layers where charge may accumulate to a level which damages the gate oxide of a connected transistor. The antenna rule compares the surface area presented by a metallic conductor connected to a gate, and the actual gate area. The antenna rule is applied by considering the metalization area of each layer. At the first of such layers, such as M1, all metalization segments which are ultimately connected to a diffusion area are not subject to the rule since the diffusion area dissipates any charge accumulating on the metal segments. The remaining segments which connect to gate connections, and have the potential for destroying the gate oxide level, are subject to the antenna rule. Multiple segments of the metalization level M1 may be connected to each other and to multiple gates. A violation occurs if the sum of commonly connected metalization areas, compared to the sum of the gate areas connected to the commonly connected metalization area exceed the established threshold. Those electrically connected metalization segments that do not pass the antenna rule risk gate failures from excessive electrostatic charge.
When the metallic conductor area on a given layer to gate area threshold is above a recognized value, the rule is violated which identifies a potential problem. The design can be changed to provide different routing and metal wiring connections to avoid the consequence of lengthy metalized lines and the resulting charge buildup.
However, the process of redesign to avoid the metal/gate area threshold violation is iterative in nature, requiring numerous changes to the metal wiring routing and several checks for each change.
The present invention utilizes the antenna rule to identify and locate metal areas which violate the rule. However, the violations once located are avoided by a process which only changes the design locally without disturbing the remaining metalization layers and circuit interconnectivity.